1. Field of the Invention
The present invention relates to a semiconductor module such as a memory module. A xe2x80x9csemiconductor modulexe2x80x9d herein refers to a module having one or more parts including a semiconductor package mounted on one substrate.
2. Description of the Background Art
Information equipment such as a personal computer has a memory module mounted as a semiconductor module. A common and conventional memory module will now be described. First, in FIG. 9, a semiconductor package 1 mounted on a memory module is shown. Semiconductor package 1 includes a package body 2 and a plurality of leads 3 protruding in parallel, respectively from opposing side portions. A dimension of semiconductor package 1 is determined by an organization for standardizing a semiconductor package, JEDEC (Joint Electron Device Engineering Council), and a xe2x80x9cTSOPxe2x80x9d (Thin Small Out-line Package) of xe2x80x9c400 milxe2x80x9d is one example. When semiconductor package 1 is an SDRAM (Synchronous Dynamic Random Access Memory), 54 pins are provided, pitch A between leads 3 is set to 0.8 mm, and width B per one lead 3 is set to 0.3 mm.
As shown in FIG. 10, a memory module 100 has semiconductor package 1 mounted on a surface of substrate 4 in a prescribed arrangement. On the surface of substrate 4, in addition to semiconductor package 1, a packaged parts 5a, 5b such as a resistance, and a buffer IC (Integrated Circuit) 6 for amplifying and timing a signal of the memory are also mounted. In order to make effective use of a limited area on substrate 4, packages are often mounted on opposing surfaces of substrate 4, as shown in FIG. 11. On both surfaces of substrate 4, pads 7 are formed in positions corresponding respectively to leads 3, which are electrically connected to pads 7 respectively. In an example shown in FIGS. 10 and 11, nine semiconductor packages 1 are mounted on one surface of substrate 4 of 133.35 mm long and 31.75 mm wide, which is a dimension determined in accordance with JEDEC standard. This means that, in total, eighteen semiconductor packages 1 are mounted on both surfaces.
As personal computers and the like are more sophisticated, an increase of memory capacity has been demanded. Accordingly, more semiconductor packages need to be mounted per one substrate. In an effort to achieve this, in Japanese Patent Laying-Open No. 4-276649, a technique to stack and mount a semiconductor package is proposed. According to the technique, as shown in FIG. 12, a semiconductor package 1e having a longer lead is prepared in addition to semiconductor package 1. As shown in FIGS. 13 and 14, a two-layered structure is provided on one surface of substrate 4. That is, an inner pad 7 having a conventional arrangement and a pad 7e arranged outside the former together form pads on the surface of substrate 4. In the two-layered structure of the semiconductor packages, lead 3 of semiconductor package 1 located on a side close to substrate 4 (hereinafter, referred to as a xe2x80x9clower layerxe2x80x9d) is connected to pad 7, while a lead 3e of semiconductor package 1e overlying the former on a side far from substrate 4 (hereinafter, referred to as an xe2x80x9cupper layerxe2x80x9d) relative to semiconductor package 1 is connected to pad 7e, going around the outside of lead 3. In this case, however, a row of pad 7e for upper layer semiconductor package 1e should be arranged parallel to, and outside, a row of pad 7 for lower layer semiconductor package 1. Therefore, width of the area occupied on substrate 4 will be larger. Consequently, for example, though nine semiconductor packages could conventionally be arranged per one layer on one surface of substrate 4, only eight semiconductor packages per one layer on one surface can be arranged, as can be seen in a memory module 101 shown in FIG. 15.
Further improved techniques are possible as described below. As shown in FIG. 16, a semiconductor package if is prepared, which is a 400 mil package having 54 pins in accordance with a conventional standard. Though pitch between leads 3f is the same as a conventional example, width C per one lead 3f is made smaller to 0.16 mm. This semiconductor package 1f is provided as a lower layer. Separately, a semiconductor package 1g is prepared having a lead 3g that has the same length as lead 3f when viewed from the top and has longer length than the same when viewed from the side. This package is provided as an upper layer. Width C per one lead 3g of semiconductor package 1g is also made smaller to 0.16 mm. Both packages are mounted, with one overlying the other, as shown in FIGS. 17 and 18. The pad of upper layer semiconductor package 1g and the pad of lower layer semiconductor package 1f are alternately arranged, and lead 3g of semiconductor package 1g is interposed between leads 3f of semiconductor package 1f respectively. Consequently, as can be seen in a memory module 102 shown in FIG. 19, nine packages can be arranged per one layer on one surface of substrate 4, as in a conventional example.
In FIG. 20, an enlarged view of the vicinity of a root portion of the lead is shown. Generally, a plurality of leads protruding in parallel from a side portion of a package body of the semiconductor package are manufactured in the following manner. A package body 2 portion is formed with resin mold so as to partially cover a leadframe 14 integrally formed. Thereafter, as shown in FIG. 21, a punch region 13 set on a dambar 12 linking each lead in a portion protruding from the side portion of package body 2 is punched through, and thus each lead is separated. In an attempt to punch the region to completely remove dambar 12 linking each lead, a puncher may strike a lead portion and damage the lead, or useful life of the puncher may be shortened. Therefore, usually, punch region 13 is set to a size covering only a main portion of dambar 12 with a small clearance from the lead portion, not exactly covering both full ends of dambar 12. Accordingly, as shown in FIG. 22, after punching, a dambar residual portion 8 will remain in the middle of lead 3. Lead 3 is folded thereafter, to have a shape shown in FIG. 23. In FIG. 23, the semiconductor package is shown, disposed on substrate 4. Here, the lead can be divided in three parts: a lead drawn-out portion 31 horizontally drawn from the side portion of package body 2; a lead extending-downward portion 32 hereinafter, referred to as a xe2x80x9clead downward portionxe2x80x9d) extending down to the surface of substrate 4; and a lead foot portion 33 for contacting pad electrode 7.
A side view of the techniques described with reference to FIGS. 16 to 19 is shown in FIG. 24. Width of the lead is made smaller in both upper and lower layers so that lead 3g of upper layer semiconductor package 1g passes a gap between leads 3f of lower layer semiconductor package 1f. In practice, however, as dambar residual portion 8 is present, the gap where lead 3g can pass is narrow. Therefore, only a slight displacement of a position of either the upper or lower semiconductor package may cause a contact of lead 3f with lead 3g. 
An object of the present invention is to provide a semiconductor module capable of increasing the mountable number of semiconductor packages per one layer on one surface of a substrate as well as avoiding contacts between leads due to a dambar residual portion.
In order to achieve the object above, a semiconductor module according to the present invention includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the lower layer semiconductor package. The lower layer semiconductor package and the upper layer semiconductor package include a package body and a plurality of leads protruding in parallel respectively from opposing side portions of the package body and electrically connected to the pad electrode. The pad electrode having the lead of the upper layer semiconductor package connected and the pad electrode having the lead of the lower layer semiconductor package connected are alternately arranged. The lead includes a lead drawn-out portion horizontally drawn from a side portion of the package body, a lead downward portion extending from the lead drawn-out portion down to a surface of the substrate and a lead foot portion continuing to a tip end of the lead downward portion and contacting the pad electrode. The lead has a dambar residual portion protruding toward the lead adjacently protruding from the same package body in any position the middle between the lead drawn-out portion and the lead downward portion. An inner surface of the lead downward portion of the upper layer semiconductor package is positioned outside an outer surface of the lead downward portion of the lower layer semiconductor package. By adopting this structure, even if slight displacement of the relative positions of upper and lower layer semiconductor packages, with one overlying the other, may occur, contact of the lead of the upper layer semiconductor package with the dambar residual portion of the lower layer semiconductor package can be prevented.
In the present invention, preferably, when viewed two-dimensionally, the pad electrode is arranged in a staggered manner so that the pad electrode connected to the upper layer semiconductor package is located outside and the pad electrode connected to the lower layer semiconductor package is located inside, with a projection region onto the substrate of the package body serving as a center. By adopting this structure, while minimizing a material for the pad electrode, a connection portion to the lead can efficiently be arranged in a limited area.
In the present invention, preferably, a horizontal distance from the package body to the dambar residual portion in the upper layer semiconductor package is substantially equal to a horizontal distance from the package body to the dambar residual portion in the lower layer semiconductor package, and the lead downward portions of the upper layer semiconductor package and the lower layer semiconductor package extend diagonally relative to the substrate. By adopting this structure, contact between the lead downward portions can be prevented, even if the lead drawn-out portions are of the same length.
In the present invention, preferably, the lead has a section including the dambar residual portion, wider than other sections. By adopting this structure, a conventional punching apparatus can be used, obviating the need of a new punching apparatus.
The present invention preferably includes a structure in which a plurality of combinations of the upper layer semiconductor package and the lower layer semiconductor package are vertically stacked. By adopting this structure, larger number of semiconductor packages can be mounted in unit area of the substrate, and a semiconductor module of high density and high performance can be obtained.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.